v_rsq_f32 GPU Native ISA AMD Vector

Vector Arithmetic

v_rsq_f32 VDST, S0

Per-lane fast approximate reciprocal square root.

Encoding

Binary Layout (AMD CDNA 5)
0111111
31:25
VDST
24:17
unassigned
16
0101110
15:9
SRC0
8:0
 

The ENC_VOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 46 in OP rebuilds 0x7E005C00, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD CDNA 4 (opcode 36, field layout), AMD CDNA 3 (opcode 36, field layout), AMD CDNA 2 (opcode 36, field layout), AMD CDNA 1 (opcode 36, field layout), AMD RDNA 3.5 (field layout), AMD RDNA 3 (field layout), AMD RDNA 2 (field layout), AMD RDNA 1 (field layout). The same in AMD RDNA 4.

Format VOP1
Width 32 bits
Opcode 46
Identifier 0x7E005C00
Execution Unit Vector ALU
Register Classes VGPR

Operands

  • VDST
    Destination VGPR
  • S0
    Source operand

GFX Target Compatibility

TargetSupport
gfx942✅ Supported
gfx1100✅ Supported

Related PTX Concepts

Special-Function Approximation ↗
equivalent with restrictions
rsqrt (PTX)
sin (PTX)
lg2 (PTX)
sqrt (PTX)
rcp (PTX)

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Calculate the reciprocal of the square root of the single-precision float input using IEEE rules and store the result into a vector register.

Semantics

VDST[lane] ≈ 1 / sqrt(S0[lane].f32) for each active lane, with a hardware-specific ULP error bound.

Example

v_rsq_f32  v1, v0   // v1 = approx(1 / sqrt(v0))

Original illustrative example, written for this site (not reproduced from a specific AMD document).

Sources