v_rsq_f32 GPU Native ISA AMD Vector

V RSQ F32 Vector Arithmetic

v_rsq_f32 VDST, S0

Per-lane fast approximate reciprocal square root.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP1) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP1
Width 32 bits
Execution Unit Vector ALU
Register Classes VGPR

Operands

  • VDST
    Destination VGPR
  • S0
    Source operand

GFX Target Compatibility

TargetSupport
gfx942✅ Supported
gfx1100✅ Supported

Related PTX Concepts

Special-Function Approximation ↗
equivalent with restrictions
rsqrt (PTX)
sin (PTX)
lg2 (PTX)
sqrt (PTX)
rcp (PTX)

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Calculate the reciprocal of the square root of the single-precision float input using IEEE rules and store the result into a vector register.

Semantics

VDST[lane] ≈ 1 / sqrt(S0[lane].f32) for each active lane, with a hardware-specific ULP error bound.

Example

v_rsq_f32  v1, v0   // v1 = approx(1 / sqrt(v0))

Original illustrative example, written for this site (not reproduced from a specific AMD document).

Sources