v_rcp_iflag_f32 GPU Native ISA AMD Vector

V RCP IFLAG F32 Vector Arithmetic

v_rcp_iflag_f32

Calculate the reciprocal of the vector float input in a manner suitable for integer division and store the result into a vector register.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP1) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP1
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Can raise integer DIV_BY_ZERO exception but cannot raise floating-point exceptions. To be used in an integer reciprocal macro by the compiler with one of the sequences listed below (depending on signed or unsigned operation). Unsigned usage: CVT_F32_U32 RCP_IFLAG_F32 MUL_F32 (2**32 - 1) CVT_U32_F32 Signed usage: CVT_F32_I32 RCP_IFLAG_F32 MUL_F32 (2**31 - 1) CVT_I32_F32

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Calculate the reciprocal of the vector float input in a manner suitable for integer division and store the result into a vector register. This opcode is intended for use as part of an integer division macro.

Semantics

D0.f32 = 1.0F / S0.f32; // Can only raise integer DIV_BY_ZERO exception

Example

v_rcp_iflag_f32 v5, v1

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources