v_sad_hi_u8 GPU Native ISA AMD Vector

V SAD HI U8 Vector Arithmetic

v_sad_hi_u8

Calculate the sum of absolute differences of elements in two packed 4-component unsigned 8-bit integer inputs, shift the sum left by 16 bits, add an…

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP3) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP3
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Overflow into the upper bits is allowed.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Calculate the sum of absolute differences of elements in two packed 4-component unsigned 8-bit integer inputs, shift the sum left by 16 bits, add an unsigned 32-bit integer value from the third input and store the result into a vector register.

Semantics

D0.u32 = (32'U(v_sad_u8(S0, S1, 0U)) << 16U) + S2.u32

Example

v_sad_hi_u8 v5, v1, v2, s3

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources