v_permlane_down_b32 GPU Native ISA AMD Vector

Vector Arithmetic

v_permlane_down_b32

AMDGPU VOP3 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)

Encoding

Binary Layout (AMD CDNA 5)
NEG
63:61
OMOD
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
110101
31:26
1001110010
25:16
CLAMP
15
OPSEL
14:11
ABS
10:8
VDST
7:0
 

The ENC_VOP3 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 626 in OP rebuilds 0x00000000D6720000, an identifier AMD lists for this encoding. No other generation in the specification defines this instruction.

Format VOP3
Width 64 bits
Opcode 626
Identifier 0x00000000D6720000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 32 bits of arbitrary data. (OPR_VGPR, FMT_NUM_B32)
  • SRC0
    Read. Operand must be a vector GPR. Uses a 9-bit operand field. Data format: 32 bits of arbitrary data. (OPR_SRC_VGPR, FMT_NUM_B32)
  • SRC1
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: 32 bits of arbitrary data. (OPR_SSRC, FMT_NUM_B32)
  • SRC2
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: 32 bits of arbitrary data. (OPR_SSRC, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP3 encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Example

v_permlane_down_b32 v5, v1, s2, s3

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx1250_asm_vop3-fake16.s). Not from an AMD document, and not authored here.

Sources