v_mul_lo_u16 GPU Native ISA AMD Vector
V MUL LO U16 Vector Arithmetic
v_mul_lo_u16
Multiply two unsigned 16-bit integer inputs and store the low bits of the result into a vector register.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (VOP2)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Supports saturation (unsigned 16-bit integer domain).
Related
More in Vector Arithmetic
Reference
AMDGPU / GFX ISA
Semantics
D0.u16 = S0.u16 * S1.u16
Example
v_mul_lo_u16 v5, v1, v2A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 180. - LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project