v_mul_hi_i32 GPU Native ISA AMD Vector

V MUL HI I32 Vector Arithmetic

v_mul_hi_i32

Multiply two signed 32-bit integer inputs and store the high 32 bits of the result into a vector register.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP3) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP3
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

To multiply integers with small magnitudes consider V_MUL_HI_I32_I24, which is intended to be a more efficient implementation.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

D0.i32 = 32'I((64'I(S0.i32) * 64'I(S1.i32)) >> 32U)

Example

v_mul_hi_i32 v5, v1, v2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources