v_mov_b32 GPU Native ISA AMD Vector

V MOV B32 Vector Arithmetic

v_mov_b32

Move 32-bit data from a vector input into a vector register.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP1) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP1
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Floating-point modifiers are valid for this instruction if S0 is a 32-bit floating point value. This instruction is suitable for negating or taking the absolute value of a floating-point value.

Related PTX Concepts

Register Move ↗
equivalent with restrictions
mov (PTX)

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

D0.b32 = S0.b32

Example

v_mov_b32 v0, v1    // Move into v0 from v1
v_mov_b32 v0, -v1   // Set v0 to the negation of v1
v_mov_b32 v0, abs(v1)   // Set v0 to the absolute value of v1

Reproduced from AMD's official "AMD Instinct MI300" ISA Reference Guide for technical accuracy.

Sources