v_minimum_f32 GPU Native ISA AMD Vector

Vector Arithmetic

v_minimum_f32

Select the IEEE minimum() of two single-precision float inputs and store the selected value into a vector register.

Encoding

Binary Layout (AMD CDNA 5)
NEG
63:61
OMOD
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
110101
31:26
1101100101
25:16
CLAMP
15
OPSEL
14:11
ABS
10:8
VDST
7:0
 

The ENC_VOP3 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 869 in OP rebuilds 0x00000000D7650000, an identifier AMD lists for this encoding. The same in AMD RDNA 4.

Format VOP3
Width 64 bits
Opcode 869
Identifier 0x00000000D7650000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 32-bit single-precision floating point value. (OPR_VGPR, FMT_NUM_F32)
  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 32-bit single-precision floating point value. (OPR_SRC, FMT_NUM_F32)
  • SRC1
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 32-bit single-precision floating point value. (OPR_SRC, FMT_NUM_F32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP3 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Example

v_minimum_f32 v5, v1, v2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx1170_asm_vop3-fake16.s). Not from an AMD document, and not authored here.

Sources