v_min3_f32 GPU Native ISA AMD Vector

Vector Arithmetic

v_min3_f32

Select the minimum of three single-precision float inputs and store the selected value into a vector register.

Also written as v_min3_num_f32. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 4)
NEG
63:61
OMOD
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
110100
31:26
0111010000
25:16
CLAMP
15
OP_SEL
14:11
ABS
10:8
VDST
7:0
 

The ENC_VOP3 layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 464 in OP rebuilds 0x00000000D1D00000, an identifier AMD lists for this encoding. Not the same in every generation: AMD RDNA 3.5 (opcode 537), AMD RDNA 3 (opcode 537), AMD RDNA 2 (opcode 337), AMD RDNA 1 (opcode 337). The same in AMD CDNA 3, AMD CDNA 2, AMD CDNA 1.

Format VOP3
Width 64 bits
Opcode 464
Identifier 0x00000000D1D00000

Operands

  • VDST
    Written. N/A Data format: N/A (OPR_VGPR, FMT_NUM_F32)
  • SRC0
    Read. N/A Data format: N/A (OPR_SRC_NOLIT, FMT_NUM_F32)
  • SRC1
    Read. N/A Data format: N/A (OPR_SRC_SIMPLE, FMT_NUM_F32)
  • SRC2
    Read. N/A Data format: N/A (OPR_SRC_SIMPLE, FMT_NUM_F32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP3 encoding (AMD CDNA 4).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

D0.f32 = v_min_f32(v_min_f32(S0.f32, S1.f32), S2.f32)

Example

v_min3_f32 v5, v1, v2, s3

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources