v_min3_f32 GPU Native ISA AMD Vector
V MIN3 F32 Vector Arithmetic
v_min3_f32
Select the minimum of three single-precision float inputs and store the selected value into a vector register.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (VOP3)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Related
More in Vector Arithmetic
Reference
AMDGPU / GFX ISA
Semantics
D0.f32 = v_min_f32(v_min_f32(S0.f32, S1.f32), S2.f32)
Example
v_min3_f32 v5, v1, v2, s3A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 340. - LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project