v_med3_i32 GPU Native ISA AMD Vector
V MED3 I32 Vector Arithmetic
v_med3_i32
Select the median of three signed 32-bit integer values and store the selected value into a vector register.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (VOP3)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Related
More in Vector Arithmetic
Reference
AMDGPU / GFX ISA
Semantics
if v_max3_i32(S0.i32, S1.i32, S2.i32) == S0.i32 then
D0.i32 = v_max_i32(S1.i32, S2.i32)
elsif v_max3_i32(S0.i32, S1.i32, S2.i32) == S1.i32 then
D0.i32 = v_max_i32(S0.i32, S2.i32)
else
D0.i32 = v_max_i32(S0.i32, S1.i32)
endif
Example
v_med3_i32 v5, v1, v2, s3A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 341. - LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project