v_med3_f32 GPU Native ISA AMD Vector

V MED3 F32 Vector Arithmetic

v_med3_f32

Select the median of three single-precision float values and store the selected value into a vector register.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP3) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP3
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

if (isNAN(64'F(S0.f32)) || isNAN(64'F(S1.f32)) || isNAN(64'F(S2.f32))) then D0.f32 = v_min3_f32(S0.f32, S1.f32, S2.f32) elsif v_max3_f32(S0.f32, S1.f32, S2.f32) == S0.f32 then D0.f32 = v_max_f32(S1.f32, S2.f32) elsif v_max3_f32(S0.f32, S1.f32, S2.f32) == S1.f32 then D0.f32 = v_max_f32(S0.f32, S2.f32) else D0.f32 = v_max_f32(S0.f32, S1.f32) endif

Example

v_med3_f32 v5, v1, v2, s3

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources