v_mbcnt_lo_u32_b32 GPU Native ISA AMD Vector

Vector Arithmetic

v_mbcnt_lo_u32_b32

For each lane 0 <= N < 32, examine the N least significant bits of the first input and count how many of those bits are "1".

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP2) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP2

Operands

  • 1: VGPR
    Vector general-purpose register, one value per lane. Written v5 in the assembler example.
  • 2: VGPR
    Vector general-purpose register, one value per lane. Written v1 in the assembler example.
  • 3: VGPR
    Vector general-purpose register, one value per lane. Written v2 in the assembler example.

Register classes read from the LLVM assembler example on this page. No source this site uses names these operands, so no names are given.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

For each lane 0 <= N < 32, examine the N least significant bits of the first input and count how many of those bits are "1". For each lane 32 <= N < 64, all "1" bits in the first input are counted. Add this count to the value in the second input and store the result into a vector register.

Example

v_mbcnt_lo_u32_b32 v5, v1, v2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources