v_min_num_f64 GPU Native ISA AMD Vector

Vector Arithmetic

v_min_num_f64

Select the IEEE minimumNumber() of two double-precision float inputs and store the selected value into a vector register.

Also written as v_min_f64. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 5)
0
31
001101
30:25
VDST
24:17
VSRC1
16:9
SRC0
8:0
 

The ENC_VOP2 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 13 in OP rebuilds 0x1A000000, an identifier AMD lists for this encoding. The same in AMD RDNA 4.

Format VOP2
Width 32 bits
Opcode 13
Identifier 0x1A000000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 64-bit double-precision floating point value. (OPR_VGPR, FMT_NUM_F64)
  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 64-bit double-precision floating point value. (OPR_SRC, FMT_NUM_F64)
  • VSRC1
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 64-bit double-precision floating point value. (OPR_VGPR, FMT_NUM_F64)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP2 encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Example

v_min_num_f64 v[5:6], -1, v[2:3]

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx1170_asm_vop2-fake16.s). Not from an AMD document, and not authored here.

Sources