v_mov_b64 GPU Native ISA AMD Vector

Vector Arithmetic

v_mov_b64

Move data from a 64-bit vector input into a vector register.

Encoding

Binary Layout (AMD CDNA 5)
0111111
31:25
VDST
24:17
unassigned
16
0011101
15:9
SRC0
8:0
 

The ENC_VOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 29 in OP rebuilds 0x7E003A00, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD CDNA 4 (opcode 56, field layout), AMD CDNA 3 (opcode 56, field layout).

Format VOP1
Width 32 bits
Opcode 29
Identifier 0x7E003A00

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 64 bits of arbitrary data. (OPR_VGPR, FMT_NUM_B64)
  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 64 bits of arbitrary data. (OPR_SRC, FMT_NUM_B64)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP1 encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Floating-point modifiers are valid for this instruction if S0.u64 is a 64-bit floating point value. This instruction is suitable for negating or taking the absolute value of a floating-point value.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

D0.b64 = S0.b64

Example

v_mov_b64 v[4:5], -1

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx1250_asm_vop1-fake16.s). Not from an AMD document, and not authored here.

Sources