v_mul_f32 GPU Native ISA AMD Vector

Vector Arithmetic

v_mul_f32 VDST, S0, S1

Per-lane single-precision floating-point multiply.

Encoding

Binary Layout (AMD CDNA 5)
0
31
001000
30:25
VDST
24:17
VSRC1
16:9
SRC0
8:0
 

The ENC_VOP2 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 8 in OP rebuilds 0x10000000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 5), AMD CDNA 3 (opcode 5), AMD CDNA 2 (opcode 5), AMD CDNA 1 (opcode 5). The same in AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3, AMD RDNA 2, AMD RDNA 1.

Format VOP2
Width 32 bits
Opcode 8
Identifier 0x10000000
Execution Unit Vector ALU
Register Classes VGPR

Operands

  • VDST
    Destination VGPR
  • S0
    First source
  • S1
    Second source

GFX Target Compatibility

TargetSupport
gfx942✅ Supported
gfx1100✅ Supported

Related PTX Concepts

Floating-Point Multiplication ↗
equivalent with restrictions
mul (PTX)

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Multiply two floating point inputs and store the result into a vector register.

Semantics

VDST[lane] = S0[lane].f32 * S1[lane].f32 for each active lane.

Example

v_mul_f32  v2, v0, v1   // per-lane v2 = v0 * v1

Original illustrative example, written for this site (not reproduced from a specific AMD document).

Sources