mul GPU Virtual ISA NVIDIA

Multiply Arithmetic

mul.mode.stype d, a, b;

Multiply two operands, selecting the low, high, or widened part of an integer product.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding — the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 1.0
Minimum Target sm_10

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations — each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
mul.mode.stype d, a, b; s16, s32, s64, u16, u32, u64 lo, hi, wide sm_10 Integer multiply; mode selects which part of the full product is written to d.
mul.f32 d, a, b; f32 sm_10 Single-precision floating-point multiply.
mul.rn.f64 d, a, b; f64 rn sm_10 Double-precision floating-point multiply with explicit round-to-nearest-even.

Operands

  • d
    Destination register
  • a
    First source operand
  • b
    Second source operand

At a Glance

Data Types f32, f64, s16, s32, s64, u16, u32, u64
Modifiers hi, lo, rn, wide

Related AMDGPU Concepts

Integer Multiplication ↗
equivalent with restrictions
s_mul_i32 (AMDGPU)
v_mul_lo_u32 (AMDGPU)
Floating-Point Multiplication ↗
equivalent with restrictions
v_mul_f32 (AMDGPU)

Reference

NVIDIA PTX ISA

Semantics

d = a * b, truncated to the selected result slice for integer forms.

Sources