fma GPU Virtual ISA NVIDIA

Fused Multiply-Add Arithmetic

fma.rn.f64 d, a, b, c;

Compute (a * b) + c with a single rounding step for improved precision over mad.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding — the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 1.4
Minimum Target sm_13

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations — each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
fma.rn.f64 d, a, b, c; f64 rn sm_13 Double-precision fused multiply-add.
fma.rn.f32 d, a, b, c; f32 rn sm_20 Single-precision fused multiply-add.

Operands

  • d
    Destination register
  • a
    Multiplicand
  • b
    Multiplier
  • c
    Addend

At a Glance

Data Types f32, f64
Modifiers rn

Related AMDGPU Concepts

Fused Multiply-Add ↗
equivalent with restrictions
v_fma_f32 (AMDGPU)

Reference

NVIDIA PTX ISA

Semantics

d = round_once(a * b + c), the product is not rounded before the addition.

Sources