add GPU Virtual ISA NVIDIA

Add Arithmetic

add.type d, a, b;

Add two operands of the same type, with optional saturation for signed 32-bit integers.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 1.0
Minimum Target sm_10

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
add.type d, a, b; s16, s32, s64, u16, u32, u64, f32, f64, f16, f16x2, bf16, bf16x2 sm_10 Generic add across integer and floating-point types.
add.sat.s32 d, a, b; s32 sat sm_10 Signed 32-bit add with saturation on overflow instead of wraparound.

Operands

  • d
    Destination register
  • a
    First source operand
  • b
    Second source operand

At a Glance

Data Types bf16, bf16x2, f16, f16x2, f32, f64, s16, s32, s64, u16, u32, u64
Modifiers sat

Related AMDGPU Concepts

Integer Addition ↗
equivalent with restrictions
s_add_u32 (AMDGPU)
v_add_u32 (AMDGPU)
Floating-Point Addition ↗
equivalent with restrictions
v_add_f32 (AMDGPU)

Related

More in Arithmetic

Reference

NVIDIA PTX ISA

Description

Performs addition and writes the resulting value into a destination register. For.u16x2,.s16x2 instruction types, forms input vectors by half word values from source operands. Half-word operands are then added in parallel to produce.u16x2,.s16x2 result in destination. For.u8x4,.s8x4 instruction types, forms input vectors by quarter word values from source operands. Quarter-word operands are then added in parallel to produce.u8x4,.s8x4 result in destination. Operands d, a and b have the same type as the instruction type. For instruction types.u16x2,.s16x2,.u8x4,.s8x4, operands d, a and b have type.b32.

Semantics

d = a + b, evaluated at the selected type's width.

Examples

@p  add.u32     x,y,z;
    add.sat.s32 c,c,1;
    add.u16x2   u,v,w;
    add.s8x4.sat p, q, r;

@p  add.rz.ftz.f32  f1,f2,f3;
add.rp.ftz.f32x2    d, a, b;

// scalar f16 additions
add.f16        d0, a0, b0;
add.rn.f16     d1, a1, b1;
add.bf16       bd0, ba0, bb0;
add.rn.bf16    bd1, ba1, bb1;
// (truncated - see the official PTX ISA docs for the full example)

.reg .f32 fc, fd;
.reg .b16 ba;
add.rz.f32.bf16.sat   fd, fa, fc;

Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.

Sources