Floating-Point Addition Arithmetic
Add two IEEE-754 floating-point operands.
Vendor-Neutral Definition
d = a + b under IEEE-754 semantics, with vendor-specific rules for rounding mode, denormal (subnormal) flushing, and NaN propagation.
⚠️ Cross-vendor mappings describe semantic relationships and are not guaranteed one-to-one compiler
translations.
equivalent with restrictions
Both compute d = a + b under IEEE-754 for single-precision float operands.
| Property | NVIDIA PTX | AMDGPU |
|---|---|---|
| Instruction | add | v_add_f32 |
| ISA Layer | Virtual | Native |
| Data Types | bf16, bf16x2, f16, f16x2, f32, f64, s16, s32, s64, u16, u32, u64 | f32 |
| Version / Target Introduced | PTX ISA 1.0 | gfx942/gfx1100 |
Important Differences
- Default rounding mode and denormal (subnormal) flush behavior are controlled per-wavefront by mode registers on AMDGPU, rather than per-instruction as with PTX's rounding-qualified forms (e.g. add.rn.f32).
Source Evidence
- Parallel Thread Execution ISA ↗ — NVIDIA Corporation
- User Guide for AMDGPU Backend ↗ — LLVM Project
Verification method: documentation