v_add_f32 GPU Native ISA AMD Vector

V ADD F32 Vector Arithmetic

v_add_f32 VDST, S0, S1

Per-lane single-precision floating-point add.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP2) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP2
Width 32 bits
Execution Unit Vector ALU
Register Classes VGPR

Operands

  • VDST
    Destination VGPR
  • S0
    First source (VGPR/SGPR/constant)
  • S1
    Second source VGPR

GFX Target Compatibility

TargetSupport
gfx942✅ Supported
gfx1100✅ Supported

Related PTX Concepts

Floating-Point Addition ↗
equivalent with restrictions
add (PTX)

Reference

AMDGPU / GFX ISA

Semantics

VDST[lane] = S0[lane].f32 + S1[lane].f32 for each active lane, per the EXEC mask.

Sources