v_add_co_ci_u32 GPU Native ISA AMD Vector

Vector Arithmetic

v_add_co_ci_u32

Add two unsigned 32-bit integer inputs and a bit from a carry-in mask, store the result into a vector register and store the carry-out mask into a…

Encoding

Binary Layout (AMD CDNA 5)
0
31
100000
30:25
VDST
24:17
VSRC1
16:9
SRC0
8:0
 

The ENC_VOP2 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 32 in OP rebuilds 0x40000000, an identifier AMD lists for this encoding. Not the same in every generation: AMD RDNA 2 (opcode 40), AMD RDNA 1 (opcode 40). The same in AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3.

Format VOP2
Width 32 bits
Opcode 32
Identifier 0x40000000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Unsigned 32-bit integral data. (OPR_VGPR, FMT_NUM_U32)
  • vcc (1)
    Written. Written in the assembly; this encoding has no field for it. 64-bit vector condition code. Data format: 64-bit mask value, read or written to a consecutive run of GPRs. The first GPR contains the least significant dword of the data. This format is generally used for lane masks and may be truncated to 32 bits when running in wave32 mode. Scalar operands with the M64 format do not have an alignment restriction when running in wave32 mode. (OPR_VCC, FMT_NUM_M64)
  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: Unsigned 32-bit integral data. (OPR_SRC, FMT_NUM_U32)
  • VSRC1
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Unsigned 32-bit integral data. (OPR_VGPR, FMT_NUM_U32)
  • vcc (2)
    Read. Written in the assembly; this encoding has no field for it. 64-bit vector condition code. Data format: 64-bit mask value, read or written to a consecutive run of GPRs. The first GPR contains the least significant dword of the data. This format is generally used for lane masks and may be truncated to 32 bits when running in wave32 mode. Scalar operands with the M64 format do not have an alignment restriction when running in wave32 mode. (OPR_VCC, FMT_NUM_M64)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP2 encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Add two unsigned 32-bit integer inputs and a bit from a carry-in mask, store the result into a vector register and store the carry-out mask into a scalar register.

Example

v_add_co_ci_u32 v1, sext(v1), sext(v4) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (wave_any.s). Not from an AMD document, and not authored here.

Sources