v_alignbyte_b32 GPU Native ISA AMD Vector

Vector Arithmetic

v_alignbyte_b32

Align a 64-bit value encoded in the first two inputs to a byte position specified in the third input, then store the result into a 32-bit vector…

Encoding

Binary Layout (AMD CDNA 5)
NEG
63:61
OMOD
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
110101
31:26
1000010111
25:16
CLAMP
15
OPSEL
14:11
ABS
10:8
VDST
7:0
 

The ENC_VOP3 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 535 in OP rebuilds 0x00000000D6170000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 463, field layout), AMD CDNA 3 (opcode 463, field layout), AMD CDNA 2 (opcode 463, field layout), AMD CDNA 1 (opcode 463, field layout), AMD RDNA 3.5 (field layout), AMD RDNA 3 (field layout), AMD RDNA 2 (opcode 335, field layout), AMD RDNA 1 (opcode 335, field layout). The same in AMD RDNA 4.

Format VOP3
Width 64 bits
Opcode 535
Identifier 0x00000000D6170000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Unsigned 32-bit integral data. (OPR_VGPR, FMT_NUM_U32)
  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: Unsigned 32-bit integral data. (OPR_SRC, FMT_NUM_U32)
  • SRC1
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: Unsigned 32-bit integral data. (OPR_SRC, FMT_NUM_U32)
  • SRC2
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: Unsigned 16-bit integral data. (OPR_SRC, FMT_NUM_U16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP3 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

 S0 carries the MSBs and S1 carries the LSBs of the value being aligned.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Align a 64-bit value encoded in the first two inputs to a byte position specified in the third input, then store the result into a 32-bit vector register.

Semantics

D0.u32 = 32'U(({ S0.u32, S1.u32 } >> (S2.u32[1 : 0] * 8U)) & 0xffffffffLL)

Example

v_alignbyte_b32 v5, v1, v2, s3

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources