v_alignbyte_b32 GPU Native ISA AMD Vector

V ALIGNBYTE B32 Vector Arithmetic

v_alignbyte_b32

Align a 64-bit value encoded in the first two inputs to a byte position specified in the third input, then store the result into a 32-bit vector…

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP3) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP3
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

 S0 carries the MSBs and S1 carries the LSBs of the value being aligned.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Align a 64-bit value encoded in the first two inputs to a byte position specified in the third input, then store the result into a 32-bit vector register.

Semantics

D0.u32 = 32'U(({ S0.u32, S1.u32 } >> (S2.u32[1 : 0] * 8U)) & 0xffffffffLL)

Example

v_alignbyte_b32 v5, v1, v2, s3

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources