v_add_co_u32 GPU Native ISA AMD Vector

V ADD CO U32 Vector Arithmetic

v_add_co_u32

Add two unsigned 32-bit integer inputs, store the result into a vector register and store the carry-out mask into a scalar register.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP2) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP2
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

In VOP3 the VCC destination may be an arbitrary SGPR-pair. Supports saturation (unsigned 32-bit integer domain).

Related PTX Concepts

Add with Carry-Out ↗
equivalent with restrictions
add.cc (PTX)

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

tmp = 64'U(S0.u32) + 64'U(S1.u32); VCC.u64[laneId] = tmp >= 0x100000000ULL ? 1'1U : 1'0U; // VCC is an UNSIGNED overflow/carry-out for V_ADDC_CO_U32. D0.u32 = tmp.u32

Example

v_add_co_u32 v5, s6, v1, v2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources