v_ashrrev_i16 GPU Native ISA AMD Vector
V ASHRREV I16 Vector Arithmetic
v_ashrrev_i16
Given a shift count in the first vector input, calculate the arithmetic shift right (preserving sign bit) of the second vector input and store the…
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (VOP2)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Related
More in Vector Arithmetic
Reference
AMDGPU / GFX ISA
Description
Given a shift count in the first vector input, calculate the arithmetic shift right (preserving sign bit) of the second vector input and store the result into a vector register.
Semantics
D0.i16 = (S1.i16 >> S0[3 : 0].u32)
Example
v_ashrrev_i16 v5, v1, v2A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 180. - LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project