v_ashrrev_i16 GPU Native ISA AMD Vector

Vector Arithmetic

v_ashrrev_i16

Given a shift count in the first vector input, calculate the arithmetic shift right (preserving sign bit) of the second vector input and store the…

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP2) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP2

Operands

  • 1: VGPR
    Vector general-purpose register, one value per lane. Written v5 in the assembler example.
  • 2: VGPR
    Vector general-purpose register, one value per lane. Written v1 in the assembler example.
  • 3: VGPR
    Vector general-purpose register, one value per lane. Written v2 in the assembler example.

Register classes read from the LLVM assembler example on this page. No source this site uses names these operands, so no names are given.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Given a shift count in the first vector input, calculate the arithmetic shift right (preserving sign bit) of the second vector input and store the result into a vector register.

Semantics

D0.i16 = (S1.i16 >> S0[3 : 0].u32)

Example

v_ashrrev_i16 v5, v1, v2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources