v_cndmask_b16 GPU Native ISA AMD Vector

Vector Arithmetic

v_cndmask_b16

Copy data from one of two inputs based on the per-lane condition code and store the result into a vector register.

Encoding

Binary Layout (AMD CDNA 5)
NEG
63:61
OMOD
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
110101
31:26
1001011101
25:16
CLAMP
15
OPSEL
14:11
ABS
10:8
VDST
7:0
 

The ENC_VOP3 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 605 in OP rebuilds 0x00000000D65D0000, an identifier AMD lists for this encoding. Not the same in every generation: AMD RDNA 3.5 (field layout), AMD RDNA 3 (field layout). The same in AMD RDNA 4.

Format VOP3
Width 64 bits
Opcode 605
Identifier 0x00000000D65D0000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 16 bits of arbitrary data. (OPR_VGPR, FMT_NUM_B16)
  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 16 bits of arbitrary data. (OPR_SRC, FMT_NUM_B16)
  • SRC1
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 16 bits of arbitrary data. (OPR_SRC, FMT_NUM_B16)
  • SRC2
    Read. Any scalar GPR operand including VCC and NULL. Data format: 64-bit mask value, read or written to a consecutive run of GPRs. The first GPR contains the least significant dword of the data. This format is generally used for lane masks and may be truncated to 32 bits when running in wave32 mode. Scalar operands with the M64 format do not have an alignment restriction when running in wave32 mode. (OPR_SREG, FMT_NUM_M64)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP3 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Example

v_cndmask_b16 v5, 0.5, -1, vcc

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources