v_cos_f16 GPU Native ISA AMD Vector
Vector Arithmetic
Calculate the trigonometric cosine of a half-precision float value using IEEE rules and store the result into a vector register.
Encoding
The ENC_VOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 97 in OP rebuilds 0x7E00C200, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD CDNA 4 (opcode 74, field layout), AMD CDNA 3 (opcode 74, field layout), AMD CDNA 2 (opcode 74, field layout), AMD CDNA 1 (opcode 74, field layout), AMD RDNA 3.5 (field layout), AMD RDNA 3 (field layout), AMD RDNA 2 (field layout), AMD RDNA 1 (field layout). The same in AMD RDNA 4.
Operands
-
VDST
Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 16-bit half-precision floating point value. (OPR_VGPR, FMT_NUM_F16) -
SRC0
Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 16-bit half-precision floating point value. (OPR_SRC, FMT_NUM_F16)
In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP1 encoding (AMD CDNA 5).
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Denormals are supported. Full range input is supported.
Related
More in Vector Arithmetic
Reference
Description
Semantics
Example
V_COS_F16(0xfc00) => 0xfe00 // cos(-INF) = NAN
V_COS_F16(0xfbff) => 0x3c00 // Most negative finite FP16
V_COS_F16(0x8000) => 0x3c00 // cos(-0.0) = 1
V_COS_F16(0x3400) => 0x0000 // cos(0.25) = 0Reproduced from AMD's official "AMD Instinct MI300" ISA Reference Guide for technical accuracy.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 210. - AMD Machine-Readable GPU ISA Specification ↗ - Advanced Micro Devices, Inc.