v_cvt_f32_i32 GPU Native ISA AMD Vector

V CVT F32 I32 Vector Arithmetic

v_cvt_f32_i32 VDST, S0

Per-lane conversion from signed 32-bit integer to single-precision float.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP1) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP1
Width 32 bits
Execution Unit Vector ALU
Register Classes VGPR

Operands

  • VDST
    Destination VGPR
  • S0
    Source VGPR (i32)

GFX Target Compatibility

TargetSupport
gfx942✅ Supported
gfx1100✅ Supported

Related PTX Concepts

Type Conversion ↗
equivalent with restrictions
cvt (PTX)

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Convert from a signed 32-bit integer input to a single-precision float value and store the result into a vector register.

Semantics

VDST[lane] = convert_i32_to_f32(S0[lane]) for each active lane.

Example

v_cvt_f32_i32  v1, v0   // per-lane v1 = (float) v0

Original illustrative example, written for this site (not reproduced from a specific AMD document).

Sources