v_cvt_f32_i32 GPU Native ISA AMD Vector

Vector Arithmetic

v_cvt_f32_i32 VDST, S0

Per-lane conversion from signed 32-bit integer to single-precision float.

Encoding

Binary Layout (AMD CDNA 5)
0111111
31:25
VDST
24:17
unassigned
16
0000101
15:9
SRC0
8:0
 

The ENC_VOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 5 in OP rebuilds 0x7E000A00, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD CDNA 4 (field layout), AMD CDNA 3 (field layout), AMD CDNA 2 (field layout), AMD CDNA 1 (field layout), AMD RDNA 3.5 (field layout), AMD RDNA 3 (field layout), AMD RDNA 2 (field layout), AMD RDNA 1 (field layout). The same in AMD RDNA 4.

Format VOP1
Width 32 bits
Opcode 5
Identifier 0x7E000A00
Execution Unit Vector ALU
Register Classes VGPR

Operands

  • VDST
    Destination VGPR
  • S0
    Source VGPR (i32)

GFX Target Compatibility

TargetSupport
gfx942✅ Supported
gfx1100✅ Supported

Related PTX Concepts

Type Conversion ↗
equivalent with restrictions
cvt (PTX)

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Convert from a signed 32-bit integer input to a single-precision float value and store the result into a vector register.

Semantics

VDST[lane] = convert_i32_to_f32(S0[lane]) for each active lane.

Example

v_cvt_f32_i32  v1, v0   // per-lane v1 = (float) v0

Original illustrative example, written for this site (not reproduced from a specific AMD document).

Sources