cvt GPU Virtual ISA NVIDIA
Convert Data Movement and Conversion Instructions
cvt.dtype.atype d, a;
Convert a value between integer and/or floating-point types with an explicit rounding mode.
Encoding
PTX is a virtual instruction set. It has no single, stable native
binary encoding - the compiler lowers this instruction to different native machine
code depending on the selected NVIDIA target architecture (compute capability).
This page intentionally shows no bit-diagram; see the target/version requirements
below for what governs how this instruction compiles.
Syntax Forms
One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.
| Syntax | Data Types | State Space(s) | Modifiers | Min. Target | Description |
|---|---|---|---|---|---|
| cvt.dtype.atype d, a; | s8, s16, s32, s64, u8, u16, u32, u64, f16, f32, f64 | sm_10 | Type conversion between the source (atype) and destination (dtype) types. | ||
| cvt.rn.f32.f64 d, a; | f32, f64 | rn, rz, rm, rp | sm_10 | Floating-point narrowing/widening conversion with explicit IEEE rounding mode. |
Operands
-
d
Destination register -
a
Source operand
At a Glance
Related AMDGPU Concepts
Related
Reference
NVIDIA PTX ISA
Description
Convert between different types and sizes.
For.f16x2 and.bf16x2 instruction type, two inputs a and b of.f32 type are
converted into.f16 or.bf16 type and the converted values are packed in the destination
register d, such that the value converted from input a is stored in the upper half of d and the value converted from input b is stored in the lower half of d
For.f16x2 instruction type, destination operand d has.f16x2 or.b32 type. For.bf16 instruction type, operand d has.b16 type. For.bf16x2 instruction type,
operand d has.b32 type. For.tf32 instruction type, operand d has.b32 type.
When converting to.e4m3x2 /.e5m2x2 data formats, the destination operand d has.b16 type. (see the official PTX ISA docs for the full description)
Semantics
d = convert(a, atype -> dtype) using the specified rounding mode; saturating forms clamp on overflow.
Examples
cvt.f32.s32 f,i;
cvt.s32.f64 j,r; // float-to-int saturates by default
cvt.rni.f32.f32 x,y; // round to nearest int, result is fp
cvt.f32.f32 x,y; // note .ftz behavior for sm_1x targets
cvt.rn.relu.f16.f32 b, f; // result is saturated with .relu saturation mode
cvt.rz.f16x2.f32 b1, f, f1; // convert two fp32 values to packed fp16 outputs
// (truncated - see the official PTX ISA docs for the full example)Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.
Sources
-
Parallel Thread Execution ISA ↗
- NVIDIA Corporation, Chapter 9 - Instruction Set
Deep-linked directly to this instruction's section.