mapa GPU Virtual ISA NVIDIA

mapa Data Movement and Conversion Instructions

mapa{.space}.type d, a, b;

Get address in the CTA specified by operand b which corresponds to the address specified by operand a.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 7.8
Minimum Target sm_90

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
mapa{.space}.type d, a, b; sm_90 Get address in the CTA specified by operand b which corresponds to the address specified by operand a. Instruction type.type indicates the type of the destination operand d and the source operand a. W (see the official PTX ISA docs for the full description)

Operands

  • d
    Destination register
  • a
    Source operand
  • b
    Source operand

At a Glance

Data Types -

Related

More in Data Movement and Conversion Instructions

Reference

NVIDIA PTX ISA

Description

Get address in the CTA specified by operand b which corresponds to the address specified by operand a. Instruction type.type indicates the type of the destination operand d and the source operand a. When space is.shared::cluster, source a is either a shared memory variable or a register containing a valid shared memory address and register d contains a shared memory address. When the optional qualifier.space is not specified, both a and d are registers containing generic addresses pointing to shared memory. b is a 32-bit integer operand representing the rank of the target CTA. Destination register d will hold an address in CTA b corresponding to operand a.

Examples

mapa.shared::cluster.u64 d1, %reg1, cta;
mapa.shared::cluster.u32 d2, sh, 3;
mapa.u64                 d3, %reg2, cta;

Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.

Sources