createpolicy GPU Virtual ISA NVIDIA
createpolicy Data Movement and Conversion Instructions
// Range-based policy
createpolicy.range{.global}.level::primary_priority{.level::secondary_priority}.b64
cache_policy, [a], primary-size, total-size;
createpolicy.range{.global}.level::primary_priority{.level::secondary_priority}.b64
cache_policy, [a], primary-size, total-size;
The createpolicy instruction creates a cache eviction policy for the specified cache level in an opaque 64-bit register specified by the destination operand cache_policy.
Encoding
PTX is a virtual instruction set. It has no single, stable native
binary encoding - the compiler lowers this instruction to different native machine
code depending on the selected NVIDIA target architecture (compute capability).
This page intentionally shows no bit-diagram; see the target/version requirements
below for what governs how this instruction compiles.
Syntax Forms
One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.
| Syntax | Data Types | State Space(s) | Modifiers | Min. Target | Description |
|---|---|---|---|---|---|
| // Range-based policy createpolicy.range{.global}.level::primary_priority{.level::secondary_priority}.b64 cache_policy, [a], primary-size, total-size; | sm_80 | The createpolicy instruction creates a cache eviction policy for the specified cache level in an opaque 64-bit register specified by the destination operand cache_policy. (see the official PTX ISA docs for the full description) |
Operands
-
Range-based policy
Operand
At a Glance
Related
Reference
NVIDIA PTX ISA
Description
The createpolicy instruction creates a cache eviction policy for the specified cache level in an
opaque 64-bit register specified by the destination operand cache_policy. The cache eviction
policy specifies how cache eviction priorities are applied to global memory addresses used in memory
operations with.level::cache_hint qualifier.
There are two types of cache eviction policies:
Range-based policy The cache eviction policy created using createpolicy.range specifies the cache eviction
behaviors for the following three address ranges: [a.. a + (primary-size - 1)] referred to as primary range. [a + primary-size.. a + (total-size - 1)] referred to as trailing secondary range. (see the official PTX ISA docs for the full description)
Examples
createpolicy.fractional.L2::evict_last.b64 policy, 1.0;
createpolicy.fractional.L2::evict_last.L2::evict_unchanged.b64 policy, 0.5;
createpolicy.range.L2::evict_last.L2::evict_first.b64
policy, [ptr], 0x100000, 0x200000;
// (truncated - see the official PTX ISA docs for the full example)Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.
Sources
-
Parallel Thread Execution ISA ↗
- NVIDIA Corporation, Chapter 9 - Instruction Set
Deep-linked directly to this instruction's section.