shfl GPU Virtual ISA NVIDIA

Shuffle Data Movement and Conversion Instructions

shfl.mode.b32 d[|p], a, b, c;

Exchange a value directly between lanes of the same warp.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 6.0
Minimum Target sm_30
Deprecation PTX ISA 6.0 (legacy non-sync form only)

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
shfl.mode.b32 d[|p], a, b, c; up, down, bfly, idx sm_30 Legacy (unsynchronized) warp shuffle; deprecated since PTX ISA 6.0 in favor of shfl.sync.
shfl.sync.mode.b32 d[|p], a, b, c, membermask; up, down, bfly, idx sm_30 Warp shuffle that also synchronizes the specified member lanes before exchanging data.

Operands

  • d
    Destination register
  • a
    Value to shuffle
  • b
    Source-lane selector
  • c
    Clamp/width control
  • membermask
    Mask of participating lanes (sync form only)

At a Glance

Data Types -
Modifiers bfly, down, idx, up

Related AMDGPU Concepts

Lane Shuffle ↗
equivalent with restrictions
ds_permute_b32 (AMDGPU)
Read Lane to Scalar Register ↗
equivalent with restrictions
v_readlane_b32 (AMDGPU)

Related

More in Data Movement and Conversion Instructions

Reference

NVIDIA PTX ISA

Description

Exchange register data between threads of a warp. shfl.sync will cause executing thread to wait until all non-exited threads corresponding to membermask have executed shfl.sync with the same qualifiers and same membermask value before resuming execution. Operand membermask specifies a 32-bit integer which is a mask indicating threads participating in barrier where the bit position corresponds to thread’s laneid. shfl.sync exchanges register data between threads in membermask. Each thread in the currently executing warp will compute a source lane index j based on input operands b and c and the mode. (see the official PTX ISA docs for the full description)

Semantics

d = value of operand a as seen by another lane in the warp, selected by mode/b; optional predicate p reports whether the source lane was valid.

Examples

shfl.sync.up.b32  Ry|p, Rx, 0x1,  0x0, 0xffffffff;

Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.

Sources