v_readfirstlane_b32 GPU Native ISA AMD Vector

V READFIRSTLANE B32 Lane Operations

v_readfirstlane_b32 SDST, S0

Read the value of a VGPR from the first active lane into a scalar register.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP1) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP1
Width 32 bits
Execution Unit Vector ALU
Register Classes VGPR, SGPR

Operands

  • SDST
    Destination SGPR
  • S0
    Source VGPR

GFX Target Compatibility

TargetSupport
gfx942✅ Supported
gfx1100✅ Supported

Related PTX Concepts

Lane Shuffle ↗
equivalent with restrictions
shfl (PTX)
Read Lane to Scalar Register ↗
equivalent with restrictions
shfl (PTX)

Related

More in Lane Operations

Reference

AMDGPU / GFX ISA

Description

Read the scalar value in the lowest active lane of the input vector register and store it into a scalar register.

Semantics

SDST = S0[first active lane in EXEC]; used to move a per-lane value into scalar (wavefront-uniform) state when all active lanes are known to agree.

Example

v_readfirstlane_b32  s0, v0   // s0 = v0 from the first active lane

Original illustrative example, written for this site (not reproduced from a specific AMD document).

Sources