v_readfirstlane_b32 GPU Native ISA AMD Vector

Lane Operations

v_readfirstlane_b32 SDST, S0

Read the value of a VGPR from the first active lane into a scalar register.

Encoding

Binary Layout (AMD CDNA 5)
0111111
31:25
VDST
24:17
unassigned
16
0000010
15:9
SRC0
8:0
 

The ENC_VOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 2 in OP rebuilds 0x7E000400, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD CDNA 4 (field layout), AMD CDNA 3 (field layout), AMD CDNA 2 (field layout), AMD CDNA 1 (field layout), AMD RDNA 3.5 (field layout), AMD RDNA 3 (field layout), AMD RDNA 2 (field layout), AMD RDNA 1 (field layout). The same in AMD RDNA 4.

Format VOP1
Width 32 bits
Opcode 2
Identifier 0x7E000400
Execution Unit Vector ALU
Register Classes VGPR, SGPR

Operands

  • SDST
    Destination SGPR
  • S0
    Source VGPR

GFX Target Compatibility

TargetSupport
gfx942✅ Supported
gfx1100✅ Supported

Related PTX Concepts

Lane Shuffle ↗
equivalent with restrictions
shfl (PTX)
Read Lane to Scalar Register ↗
equivalent with restrictions
shfl (PTX)

Related

More in Lane Operations

Reference

AMDGPU / GFX ISA

Description

Read the scalar value in the lowest active lane of the input vector register and store it into a scalar register.

Semantics

SDST = S0[first active lane in EXEC]; used to move a per-lane value into scalar (wavefront-uniform) state when all active lanes are known to agree.

Example

v_readfirstlane_b32  s0, v0   // s0 = v0 from the first active lane

Original illustrative example, written for this site (not reproduced from a specific AMD document).

Sources