v_bcnt_u32_b32 GPU Native ISA AMD Vector

V BCNT U32 B32 Lane Operations

v_bcnt_u32_b32 VDST, S0, S1

Per-lane accumulating population count.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP3) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP3
Width 32 bits
Execution Unit Vector ALU
Register Classes VGPR

Operands

  • VDST
    Destination VGPR
  • S0
    Value to count bits in
  • S1
    Accumulator operand

GFX Target Compatibility

TargetSupport
gfx942✅ Supported
gfx1100✅ Supported

Related PTX Concepts

Population Count ↗
equivalent with restrictions
popc (PTX)

Related

More in Lane Operations

Reference

AMDGPU / GFX ISA

Description

Count the number of "1" bits in the vector input and store the result into a vector register.

Semantics

VDST[lane] = popcount(S0[lane]) + S1[lane] for each active lane; pass a zero S1 to match a plain population count.

Example

v_bcnt_u32_b32  v1, v0, 0   // v1 = popcount(v0) + 0

Original illustrative example, written for this site (not reproduced from a specific AMD document).

Sources