v_bcnt_u32_b32 GPU Native ISA AMD Vector

Lane Operations

v_bcnt_u32_b32 VDST, S0, S1

Per-lane accumulating population count.

Encoding

Binary Layout (AMD CDNA 5)
NEG
63:61
OMOD
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
110101
31:26
1100011110
25:16
CLAMP
15
OPSEL
14:11
ABS
10:8
VDST
7:0
 

The ENC_VOP3 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 798 in OP rebuilds 0x00000000D71E0000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 651, field layout), AMD CDNA 3 (opcode 651, field layout), AMD CDNA 2 (opcode 651, field layout), AMD CDNA 1 (opcode 651, field layout), AMD RDNA 3.5 (field layout), AMD RDNA 3 (field layout), AMD RDNA 2 (opcode 868, field layout), AMD RDNA 1 (opcode 868, field layout). The same in AMD RDNA 4.

Format VOP3
Width 64 bits
Opcode 798
Identifier 0x00000000D71E0000
Execution Unit Vector ALU
Register Classes VGPR

Operands

  • VDST
    Destination VGPR
  • S0
    Value to count bits in
  • S1
    Accumulator operand

GFX Target Compatibility

TargetSupport
gfx942✅ Supported
gfx1100✅ Supported

Related PTX Concepts

Population Count ↗
equivalent with restrictions
popc (PTX)

Related

More in Lane Operations

Reference

AMDGPU / GFX ISA

Description

Count the number of "1" bits in the vector input and store the result into a vector register.

Semantics

VDST[lane] = popcount(S0[lane]) + S1[lane] for each active lane; pass a zero S1 to match a plain population count.

Example

v_bcnt_u32_b32  v1, v0, 0   // v1 = popcount(v0) + 0

Original illustrative example, written for this site (not reproduced from a specific AMD document).

Sources