isspacep GPU Virtual ISA NVIDIA

isspacep Data Movement and Conversion Instructions

isspacep.space p, a; // result is .pred

Write predicate register p with 1 if generic address a falls within the specified state space window and with 0 otherwise.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 2.0
Minimum Target sm_20

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
isspacep.space p, a; // result is .pred sm_20 Write predicate register p with 1 if generic address a falls within the specified state space window and with 0 otherwise. (see the official PTX ISA docs for the full description)

Operands

At a Glance

Data Types -

Related

More in Data Movement and Conversion Instructions

Reference

NVIDIA PTX ISA

Description

Write predicate register p with 1 if generic address a falls within the specified state space window and with 0 otherwise. Destination p has type.pred; the source address operand must be of type.u32 or.u64. isspacep.param{::entry} returns 1 if the generic address falls within the window of Kernel Function Parameters, otherwise returns 0. If.param is specified without any sub-qualifiers then it defaults to.param::entry. isspacep.global returns 1 for Kernel Function Parameters as.param window is contained within the.global window. If no sub-qualifier is specified with.shared state space, then::cta is assumed by default. Note ispacep. (see the official PTX ISA docs for the full description)

Examples

isspacep.const           iscnst, cptr;
isspacep.global          isglbl, gptr;
isspacep.local           islcl,  lptr;
isspacep.shared          isshrd, sptr;
isspacep.param::entry    isparam, pptr;
isspacep.shared::cta     isshrdcta, sptr;
// (truncated - see the official PTX ISA docs for the full example)

Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.

Sources