multimem.st.async GPU Virtual ISA NVIDIA
multimem.st.async Data Movement and Conversion Instructions
multimem.st.async.sem.scope{.ss}.type [a], b;
multimem.st.async is a non-blocking instruction which initiates an asynchronous store operation that stores the value specified by source operand b to the memory locations residing on each GPU’s memory referred to by the destination multimem address operand a.
Encoding
PTX is a virtual instruction set. It has no single, stable native
binary encoding - the compiler lowers this instruction to different native machine
code depending on the selected NVIDIA target architecture (compute capability).
This page intentionally shows no bit-diagram; see the target/version requirements
below for what governs how this instruction compiles.
Syntax Forms
One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.
| Syntax | Data Types | State Space(s) | Modifiers | Min. Target | Description |
|---|---|---|---|---|---|
| multimem.st.async.sem.scope{.ss}.type [a], b; | sm_90 | multimem.st.async is a non-blocking instruction which initiates an asynchronous store operation that stores the value specified by source operand b to the memory locations residing on each GPU’s memor… (see the official PTX ISA docs for the full description) |
Operands
At a Glance
Related
Reference
NVIDIA PTX ISA
Description
multimem.st.async is a non-blocking instruction which initiates an asynchronous store
operation that stores the value specified by source operand b to the memory locations
residing on each GPU’s memory referred to by the destination multimem address operand a.
Address operand a must be a multimem address. Otherwise, the behavior is undefined.
Examples
// Release store to multimem address, GPU scope, explicit .global state space.
multimem.st.async.release.gpu.global.u32 [mm_addr], src_u32;
// Release store, system scope, generic addressing for multimem operand.
multimem.st.async.release.sys.f64 [mm_addr], src_f64;Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.
Sources
-
Parallel Thread Execution ISA ↗
- NVIDIA Corporation, Chapter 9 - Instruction Set
Deep-linked directly to this instruction's section.