spdecompress GPU Virtual ISA NVIDIA
Data Movement and Conversion Instructions
spdecompress.elemsize.idxsize.spfactor.num data, mdata, cdata;
The spdecompress instruction copies elements from structured sparse compressed vector cdata to form the dense vector data.
Encoding
PTX is a virtual instruction set. It has no single, stable native
binary encoding - the compiler lowers this instruction to different native machine
code depending on the selected NVIDIA target architecture (compute capability).
This page intentionally shows no bit-diagram; see the target/version requirements
below for what governs how this instruction compiles.
Syntax Forms
One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.
| Syntax | Data Types | State Space(s) | Modifiers | Min. Target | Description |
|---|---|---|---|---|---|
| spdecompress.elemsize.idxsize.spfactor.num data, mdata, cdata; | sm_107a | The spdecompress instruction copies elements from structured sparse compressed vector cdata to form the dense vector data. (see the official PTX ISA docs for the full description) |
Operands
-
data
Operand -
mdata
Operand -
cdata
Operand
At a Glance
Related
Reference
NVIDIA PTX ISA
Description
The spdecompress instruction copies elements from structured sparse compressed vector cdata to form the dense vector data. The metadata information corresponding to
the structured sparse compressed vector cdata is given by the vector operand mdata.
The decompression factor is derived from the qualifier .spfactor. The qualifier is of
form .sp::num_src:num_target implying instruction decompresses each sequence of num_src elements so as to form the sequence comprising num_target many elements.
Given decompress operation, it naturally follows that the num_src value must be
strictly numerically smaller than the num_target value. (see the official PTX ISA docs for the full description)
Semantics
for N in .num:
for S in num_source:
data[mdata[N][S]] = cdata[N][S];
Examples
.reg .b32 mdata_<4>, cdata_<32>, data_<32>;
spdecompress.b8.b2.sp::2:4.x32 {data_0, data_1, data_2, data_3, data_4, data_5, data_6, data_7, data_8,
data_9, data_10, data_11, data_12, data_13, data_14, data_15, data_17,
data_18, data_19, data_20, data_21, data_22, data_23, data_24, data_25,
data_26, data_27, data_28, data_29, data_30, data_31},
// (truncated - see the official PTX ISA docs for the full example)Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.
Sources
-
Parallel Thread Execution ISA ↗
- NVIDIA Corporation, Chapter 9 - Instruction Set
Deep-linked directly to this instruction's section.