prefetchu GPU Virtual ISA NVIDIA

prefetchu Data Movement and Conversion Instructions

prefetchu.L1 [a]; // prefetch to uniform cache

The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level. A prefetch to a shared memory location performs no operation.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 2.0
Minimum Target sm_20

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
prefetchu.L1 [a]; // prefetch to uniform cache sm_20 The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level. A prefetch to a shared memory location performs no operation.

Operands

At a Glance

Data Types -

Related AMDGPU Concepts

Cache Prefetch ↗
equivalent with restrictions
flat_prefetch_b8 (AMDGPU)

Related

More in Data Movement and Conversion Instructions

Reference

NVIDIA PTX ISA

Examples

prefetch.global.L1             [ptr];
prefetch.global.L2::evict_last [ptr];
prefetchu.L1  [addr];
prefetch.const.tensormap       [ptr];

Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.

Sources