Cache Prefetch Memory

Hint the memory system to bring a cache line into a specified cache level ahead of an anticipated access, without producing a register result.

Vendor-Neutral Definition

Cache[address] is fetched into the specified cache level as a hint; has no architectural effect on register state and does not block on completion.
⚠️ Cross-vendor mappings describe semantic relationships and are not guaranteed one-to-one compiler translations.
equivalent with restrictions Both hint the memory system to bring a cache line into cache ahead of an anticipated access, with no architectural effect on register state.
Property NVIDIA PTX AMDGPU
Instruction prefetch, prefetchu global_prefetch_b8, flat_prefetch_b8
ISA Layer Virtual Native
Data Types - b8
Version / Target Introduced PTX ISA 2.0, PTX ISA 2.0 -

Important Differences

  • PTX's prefetch supports selecting a specific cache level (.L1/.L2) as a modifier; the AMDGPU prefetch instructions in this dataset are per-address-space (global vs. flat aperture) rather than per-cache-level, so the exact cache-level targeting behavior should be checked against AMD's documentation rather than assumed to match PTX's modifier one-for-one.

Source Evidence

Verification method: documentation