applypriority.async.bulk GPU Virtual ISA NVIDIA

Data Movement and Conversion Instructions

applypriority.async.bulk{.src}.completion_mechanism.level::eviction_priority [a], size;

The applypriority.async.bulk instruction applies the cache eviction priority specified by the .level::eviction_priority qualifier to the address range [a..a+size) in the specified cache level.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 9.4
Minimum Target sm_107f

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
applypriority.async.bulk{.src}.completion_mechanism.level::eviction_priority [a], size; sm_107f The applypriority.async.bulk instruction applies the cache eviction priority specified by the .level::eviction_priority qualifier to the address range [a..a+size) in the specified cache level. (see the official PTX ISA docs for the full description)

Operands

At a Glance

Data Types -

Related

More in Data Movement and Conversion Instructions

Reference

NVIDIA PTX ISA

Description

The applypriority.async.bulk instruction applies the cache eviction priority specified by the .level::eviction_priority qualifier to the address range [a..a+size) in the specified cache level. If no state space is specified then Generic Addressing is used. If the specified address does not fall within the address window of .global state space then the behavior is undefined. The operand size is a 32 bit integer that specifies the amount of data, in bytes, in the specified cache level on which the priority is to be applied. The value of the size operand needs to be a multiple of 16. Supported addressing modes for operand a are described in Addresses as Operands. a must be aligned to 128 bytes. (see the official PTX ISA docs for the full description)

Examples

applypriority.async.bulk.global.bulk_group.L2::evict_normal [ptr], 128;

Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.

Sources