applypriority GPU Virtual ISA NVIDIA
applypriority Data Movement and Conversion Instructions
applypriority{.global}.level::eviction_priority [a], size;
The applypriority instruction applies the cache eviction priority specified by the.level::eviction_priority qualifier to the address range [a..a+size)
Encoding
PTX is a virtual instruction set. It has no single, stable native
binary encoding - the compiler lowers this instruction to different native machine
code depending on the selected NVIDIA target architecture (compute capability).
This page intentionally shows no bit-diagram; see the target/version requirements
below for what governs how this instruction compiles.
Syntax Forms
One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.
| Syntax | Data Types | State Space(s) | Modifiers | Min. Target | Description |
|---|---|---|---|---|---|
| applypriority{.global}.level::eviction_priority [a], size; | sm_80 | The applypriority instruction applies the cache eviction priority specified by the.level::eviction_priority qualifier to the address range [a..a+size) in the specified cache level. (see the official PTX ISA docs for the full description) |
Operands
At a Glance
Related
Reference
NVIDIA PTX ISA
Description
The applypriority instruction applies the cache eviction priority specified by the.level::eviction_priority qualifier to the address range [a..a+size) in the specified cache
level.
If no state space is specified then Generic Addressing is
used. If the specified address does not fall within the address window of.global state space
then the behavior is undefined.
The operand size is an integer constant that specifies the amount of data, in bytes, in the
specified cache level on which the priority is to be applied. The only supported value for the size operand is 128.
Supported addressing modes for operand a are described in Addresses as Operands. a must be aligned to 128 bytes.
Examples
applypriority.global.L2::evict_normal [ptr], 128;Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.
Sources
-
Parallel Thread Execution ISA ↗
- NVIDIA Corporation, Chapter 9 - Instruction Set
Deep-linked directly to this instruction's section.