mov GPU Virtual ISA NVIDIA

Move Data Movement and Conversion Instructions

mov.type d, a;

Copy a value into a register, or materialize an address/immediate.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 1.0
Minimum Target sm_10

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
mov.type d, a; b16, b32, b64, s16, s32, s64, u16, u32, u64, f32, f64, pred sm_10 Register-to-register move, or load of an immediate/address.

Operands

  • d
    Destination register
  • a
    Source (register, immediate, or address expression)

At a Glance

Data Types b16, b32, b64, f32, f64, pred, s16, s32, s64, u16, u32, u64

Related AMDGPU Concepts

Register Move ↗
equivalent with restrictions
v_mov_b32 (AMDGPU)
s_mov_b32 (AMDGPU)

Related

More in Data Movement and Conversion Instructions

Reference

NVIDIA PTX ISA

Description

Write register d with the value of a. Operand a may be a register, special register, variable with optional offset in an addressable memory space, or function name. For variables declared in.const,.global,.local, and.shared state spaces, mov places the non-generic address of the variable (i.e., the address of the variable in its state space) into the destination register. (see the official PTX ISA docs for the full description)

Semantics

d = a, no type conversion is performed.

Examples

mov.f32  d,a;
mov.u16  u,v;
mov.f32  k,0.1;
mov.u32  ptr, A;        // move address of A into ptr
mov.u32  ptr, A[5];     // move address of A[5] into ptr
mov.u32  ptr, A+20;     // move address with offset into ptr
// (truncated - see the official PTX ISA docs for the full example)

mov.b32 %r1,{a,b};      // a,b have type .u16
mov.b64 {lo,hi}, %x;    // %x is a double; lo,hi are .u32
mov.b32 %r1,{x,y,z,w};  // x,y,z,w have type .b8
mov.b32 {r,g,b,a},%r1;  // r,g,b,a have type .u8
mov.b64 {%r1, _}, %x;   // %x is.b64, %r1 is .b32
mov.b128 {%b1, %b2}, %y;   // %y is.b128, %b1 and % b2 are .b64
// (truncated - see the official PTX ISA docs for the full example)

Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.

Sources