discard GPU Virtual ISA NVIDIA
discard Data Movement and Conversion Instructions
discard{.global}.level [a], size;
Semantically, this behaves like a weak write of an unstable indeterminate value: reads of memory locations with unstable indeterminate values may return different bit patterns each time until the memory is overwritten.
Encoding
PTX is a virtual instruction set. It has no single, stable native
binary encoding - the compiler lowers this instruction to different native machine
code depending on the selected NVIDIA target architecture (compute capability).
This page intentionally shows no bit-diagram; see the target/version requirements
below for what governs how this instruction compiles.
Syntax Forms
One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.
| Syntax | Data Types | State Space(s) | Modifiers | Min. Target | Description |
|---|---|---|---|---|---|
| discard{.global}.level [a], size; | sm_80 | Semantically, this behaves like a weak write of an unstable indeterminate value: reads of memory locations with unstable indeterminate values may return different bit patterns each time until the memo… (see the official PTX ISA docs for the full description) |
Operands
At a Glance
Related
Reference
NVIDIA PTX ISA
Description
Semantically, this behaves like a weak write of an unstable indeterminate value:
reads of memory locations with unstable indeterminate values may return different
bit patterns each time until the memory is overwritten.
This operation hints to the implementation that data in the specified cache.level can be destructively discarded without writing it back to memory.
The operand size is an integer constant that specifies the length in bytes of the
address range [a, a + size) to write unstable indeterminate values into.
The only supported value for the size operand is 128.
If no state space is specified then Generic Addressing is used. (see the official PTX ISA docs for the full description)
Examples
discard.global.L2 [ptr], 128;
ld.weak.u32 r0, [ptr];
ld.weak.u32 r1, [ptr];
// The values in r0 and r1 may differ!Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.
Sources
-
Parallel Thread Execution ISA ↗
- NVIDIA Corporation, Chapter 9 - Instruction Set
Deep-linked directly to this instruction's section.