v_readlane_b32 GPU Native ISA AMD Vector

Vector Arithmetic

v_readlane_b32

Read the scalar value in the specified lane of the first input where the lane select is in the second input. Store the result into a scalar register.

Encoding

Binary Layout (AMD CDNA 5)
NEG
63:61
OMOD
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
110101
31:26
1101100000
25:16
CLAMP
15
OPSEL
14:11
ABS
10:8
VDST
7:0
 

The ENC_VOP3 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 864 in OP rebuilds 0x00000000D7600000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 649, field layout), AMD CDNA 3 (opcode 649, field layout), AMD CDNA 2 (opcode 649, field layout), AMD CDNA 1 (opcode 649, field layout), AMD RDNA 3.5 (field layout), AMD RDNA 3 (field layout), AMD RDNA 2 (field layout), AMD RDNA 1 (field layout). The same in AMD RDNA 4.

Format VOP2
Width 64 bits
Opcode 864
Identifier 0x00000000D7600000

Operands

  • VDST
    Written. Any scalar GPR operand including VCC and NULL. Data format: 32 bits of arbitrary data. (OPR_SREG, FMT_NUM_B32)
  • SRC0
    Read. Operand must be a vector GPR. Uses a 9-bit operand field. Data format: 32 bits of arbitrary data. (OPR_SRC_VGPR, FMT_NUM_B32)
  • SRC1
    Read. Operand is legal for a lane-select operand, generally scalar integer values in the range 0..63. Data format: 32 bits of arbitrary data. (OPR_SSRC_LANESEL, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP3 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related PTX Concepts

Read Lane to Scalar Register ↗
equivalent with restrictions
shfl (PTX)

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Example

v_readlane_b32 s5, v1, s2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources