v_permlanex16_b32 GPU Native ISA AMD Vector

Vector Arithmetic

v_permlanex16_b32

Perform arbitrary gather-style operation across two rows (each row is 16 contiguous lanes).

Encoding

Binary Layout (AMD CDNA 5)
NEG
63:61
OMOD
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
110101
31:26
1001011100
25:16
CLAMP
15
OPSEL
14:11
ABS
10:8
VDST
7:0
 

The ENC_VOP3 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 604 in OP rebuilds 0x00000000D65C0000, an identifier AMD lists for this encoding. Not the same in every generation: AMD RDNA 3.5 (field layout), AMD RDNA 3 (field layout), AMD RDNA 2 (opcode 888, field layout), AMD RDNA 1 (opcode 888, field layout). The same in AMD RDNA 4.

Format VOP3
Width 64 bits
Opcode 604
Identifier 0x00000000D65C0000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 32 bits of arbitrary data. (OPR_VGPR, FMT_NUM_B32)
  • SRC0
    Read. Operand must be a vector GPR. Uses a 9-bit operand field. Data format: 32 bits of arbitrary data. (OPR_SRC_VGPR, FMT_NUM_B32)
  • SRC1
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: 32 bits of arbitrary data. (OPR_SSRC, FMT_NUM_B32)
  • SRC2
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: 32 bits of arbitrary data. (OPR_SSRC, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP3 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Example

v_permlanex16_b32 v5, v1, s2, s3

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources