v_permlanex16_b32 GPU Native ISA AMD Vector
V PERMLANEX16 B32 Vector Arithmetic
v_permlanex16_b32
Perform arbitrary gather-style operation across two rows (each row is 16 contiguous lanes).
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (VOP3)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Related
More in Vector Arithmetic
Reference
AMDGPU / GFX ISA
Example
v_permlanex16_b32 v5, v1, s2, s3A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
- AMD Machine-Readable GPU ISA Specification ↗ - Advanced Micro Devices, Inc.
- LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project