v_prng_b32 GPU Native ISA AMD Vector

Vector Arithmetic

v_prng_b32

Generate a pseudorandom number using an LFSR (linear feedback shift register) seeded with the vector input, then store the result into a vector…

Encoding

Binary Layout (AMD CDNA 5)
0111111
31:25
VDST
24:17
unassigned
16
1001011
15:9
SRC0
8:0
 

The ENC_VOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 75 in OP rebuilds 0x7E009600, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD CDNA 4 (opcode 88, field layout).

Format VOP1
Width 32 bits
Opcode 75
Identifier 0x7E009600

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 32 bits of arbitrary data. (OPR_VGPR, FMT_NUM_B32)
  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 32 bits of arbitrary data. (OPR_SRC, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP1 encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Generate a pseudorandom number using an LFSR (linear feedback shift register) seeded with the vector input, then store the result into a vector register.

Example

v_prng_b32 v5, v1

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx1250_asm_vop1-fake16.s). Not from an AMD document, and not authored here.

Sources