v_perm_b32 GPU Native ISA AMD Vector

Vector Arithmetic

v_perm_b32

Permute a 64-bit value constructed from two vector inputs (most significant bits come from the first input) using a per-lane selector from the third…

Encoding

Binary Layout (AMD CDNA 5)
NEG
63:61
OMOD
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
110101
31:26
1001000100
25:16
CLAMP
15
OPSEL
14:11
ABS
10:8
VDST
7:0
 

The ENC_VOP3 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 580 in OP rebuilds 0x00000000D6440000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 493, field layout), AMD CDNA 3 (opcode 493, field layout), AMD CDNA 2 (opcode 493, field layout), AMD CDNA 1 (opcode 493, field layout), AMD RDNA 3.5 (field layout), AMD RDNA 3 (field layout), AMD RDNA 2 (opcode 836, field layout), AMD RDNA 1 (opcode 836, field layout). The same in AMD RDNA 4.

Format VOP3
Width 64 bits
Opcode 580
Identifier 0x00000000D6440000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 8 bits of arbitrary data. Packed 4-component value. (OPR_VGPR, FMT_NUM_PK4_B8)
  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 32 bits of arbitrary data. (OPR_SRC, FMT_NUM_B32)
  • SRC1
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 32 bits of arbitrary data. (OPR_SRC, FMT_NUM_B32)
  • SRC2
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: Unsigned 8-bit integral data. Packed 4-component value. (OPR_SRC, FMT_NUM_PK4_U8)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP3 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Selects 0 through 7 select the corresponding byte of the 64-bit input value. Selects 8 through 11 are useful in modeling sign extension of a smaller-precision signed integer to a larger- precision result by replicating the leading bit of a selected byte. Selects 12 and 13 return padding values of 0 and 1 bits respectively. Note the MSBs of the 64-bit value being selected are stored in S0. This is counterintuitive for a little-endian architecture.

Related PTX Concepts

Byte Permute ↗
equivalent with restrictions
prmt (PTX)

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Permute a 64-bit value constructed from two vector inputs (most significant bits come from the first input) using a per-lane selector from the third input. The lane selector allows each byte of the result to choose from any of the 8 input bytes, perform sign extension or pad with 0/1 bits. Store the result into a vector register.

Semantics

BYTE_PERMUTE = lambda(data, sel) ( declare in : 8'B[8]; for i in 0 : 7 do in[i] = data[i * 8 + 7 : i * 8].b8 endfor; if sel.u32 >= 13U then return 8'0xff elsif sel.u32 == 12U then return 8'0x0 elsif sel.u32 == 11U then return in[7][7].b8 * 8'0xff elsif sel.u32 == 10U then return in[5][7].b8 * 8'0xff elsif sel.u32 == 9U then return in[3][7].b8 * 8'0xff elsif sel.u32 == 8U then return in[1][7].b8 * 8'0xff else return in[sel] endif); D0[31 : 24] = BYTE_PERMUTE({ S0.u32, S1.u32 }, S2.u32[31 : 24]); D0[23 : 16] = BYTE_PERMUTE({ S0.u32, S1.u32 }, S2.u32[23 : 16]); D0[15 : 8] = BYTE_PERMUTE({ S0.u32, S1.u32 }, S2.u32[15 : 8]); D0[7 : 0] = BYTE_PERMUTE({ S0.u32, S1.u32 }, S2.u32[7 : 0])

Example

v_perm_b32 v5, v1, v2, s3

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources