v_mul_hi_u32_u24 GPU Native ISA AMD Vector

Vector Arithmetic

v_mul_hi_u32_u24

Multiply two unsigned 24-bit integer inputs and store the high 32 bits of the result as an unsigned 32-bit integer into a vector register.

Encoding

Binary Layout (AMD CDNA 5)
0
31
001100
30:25
VDST
24:17
VSRC1
16:9
SRC0
8:0
 

The ENC_VOP2 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 12 in OP rebuilds 0x18000000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 9), AMD CDNA 3 (opcode 9), AMD CDNA 2 (opcode 9), AMD CDNA 1 (opcode 9). The same in AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3, AMD RDNA 2, AMD RDNA 1.

Format VOP2
Width 32 bits
Opcode 12
Identifier 0x18000000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Unsigned 32-bit integral data. (OPR_VGPR, FMT_NUM_U32)
  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: Unsigned 32-bit integral data. (OPR_SRC, FMT_NUM_U32)
  • VSRC1
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Unsigned 32-bit integral data. (OPR_VGPR, FMT_NUM_U32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP2 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

See also V_MUL_U32_U24.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

D0.u32 = 32'U((64'U(S0.u24) * 64'U(S1.u24)) >> 32U)

Example

v_mul_hi_u32_u24 v5, -1, v2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources