v_permlane16_var_b32 GPU Native ISA AMD Vector

Vector Arithmetic

v_permlane16_var_b32

Perform arbitrary gather-style operation within a row (16 contiguous lanes).

Encoding

Binary Layout (AMD CDNA 5)
NEG
63:61
OMOD
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
110101
31:26
1100001111
25:16
CLAMP
15
OPSEL
14:11
ABS
10:8
VDST
7:0
 

The ENC_VOP3 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 783 in OP rebuilds 0x00000000D70F0000, an identifier AMD lists for this encoding. The same in AMD RDNA 4.

Format VOP3
Width 64 bits
Opcode 783
Identifier 0x00000000D70F0000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 32 bits of arbitrary data. (OPR_VGPR, FMT_NUM_B32)
  • SRC0
    Read. Operand must be a vector GPR. Uses a 9-bit operand field. Data format: 32 bits of arbitrary data. (OPR_SRC_VGPR, FMT_NUM_B32)
  • SRC1
    Read. Operand must be a vector GPR. Uses a 9-bit operand field. Data format: 32 bits of arbitrary data. (OPR_SRC_VGPR, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP3 encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Sources