v_mul_lo_u32 GPU Native ISA AMD Vector

Vector Arithmetic

v_mul_lo_u32 VDST, S0, S1

Per-lane 32-bit unsigned multiply, low half of the product.

Encoding

Binary Layout (AMD CDNA 5)
NEG
63:61
OMOD
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
110101
31:26
1100101100
25:16
CLAMP
15
OPSEL
14:11
ABS
10:8
VDST
7:0
 

The ENC_VOP3 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 812 in OP rebuilds 0x00000000D72C0000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 645, field layout), AMD CDNA 3 (opcode 645, field layout), AMD CDNA 2 (opcode 645, field layout), AMD CDNA 1 (opcode 645, field layout), AMD RDNA 3.5 (field layout), AMD RDNA 3 (field layout), AMD RDNA 2 (opcode 361, field layout), AMD RDNA 1 (opcode 361, field layout). The same in AMD RDNA 4.

Format VOP3
Width 64 bits
Opcode 812
Identifier 0x00000000D72C0000
Execution Unit Vector ALU
Register Classes VGPR

Operands

  • VDST
    Destination VGPR
  • S0
    First source
  • S1
    Second source

GFX Target Compatibility

TargetSupport
gfx942✅ Supported
gfx1100✅ Supported

Related PTX Concepts

Integer Multiplication ↗
equivalent with restrictions
mul (PTX)

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Multiply two unsigned 32-bit integer inputs and store the result into a vector register.

Semantics

VDST[lane] = lo32(S0[lane].u32 * S1[lane].u32) for each active lane.

Example

v_mul_lo_u32  v2, v0, v1   // per-lane low 32 bits of v0 * v1

Original illustrative example, written for this site (not reproduced from a specific AMD document).

Sources