v_mul_lo_u32 GPU Native ISA AMD Vector

V MUL LO U32 Vector Arithmetic

v_mul_lo_u32 VDST, S0, S1

Per-lane 32-bit unsigned multiply, low half of the product.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP3) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP3
Width 32 bits
Execution Unit Vector ALU
Register Classes VGPR

Operands

  • VDST
    Destination VGPR
  • S0
    First source
  • S1
    Second source

GFX Target Compatibility

TargetSupport
gfx942✅ Supported
gfx1100✅ Supported

Related PTX Concepts

Integer Multiplication ↗
equivalent with restrictions
mul (PTX)

Reference

AMDGPU / GFX ISA

Semantics

VDST[lane] = lo32(S0[lane].u32 * S1[lane].u32) for each active lane.

Sources