v_mul_hi_i32_i24 GPU Native ISA AMD Vector

V MUL HI I32 I24 Vector Arithmetic

v_mul_hi_i32_i24

Multiply two signed 24-bit integer inputs and store the high 32 bits of the result as a signed 32-bit integer into a vector register.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP2) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP2
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

See also V_MUL_I32_I24.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

D0.i32 = 32'I((64'I(S0.i24) * 64'I(S1.i24)) >> 32U)

Example

v_mul_hi_i32_i24 v5, -1, v2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources